The world of computer technology

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CPU

During the process, the processor reads the sequence of instructions contained in memory, and executes them. Such a sequence of instructions called a program and is a useful algorithm of the processor. Priority reading instruction varies if the processor reads the jump command - then address the following commands may be different. Another example of a process change is the case of receiving a stop command or switch to a hardware interrupt processing.

Command of the CPU is the lowest level of computer control, so the performance of each team will inevitably and surely. Not performed any validation of actions performed, in particular, does not check the possible loss of valuable data. For the computer to perform only valid actions, the team must be properly organized in a desired program. The rate of transition from one phase to another cycle of the clock generator. Clock generator generates pulses that serve to beat the CPU. The frequency of clock is called clock speed.

The main characteristics of the processors are bit and speed.
Performance - a parameter indicating the number of cycles performed by the processor in the second. Measured in megahertz (MHz), 1 MHz = 1 million cycles per second. Than this parameter above the faster processor.
Bit - a parameter which is important for such devices in the computer as the internal registers, the bus input output data bus memory addresses.
Types of processors:

CISC-processors

Complex Instruction Set Computing - computing with complex instruction set. Processor architecture, based on complication instruction set. Typical representatives of CISC is a family of microprocessors Intel x86 (although for many years, these processors are CISC only on the external system commands).
RISC-processor

Reduced Instruction Set Computing (technology) - reduced instruction set computing. Processor architecture, built on the basis of a reduced set of commands. Characterized by the presence of fixed length instructions, a large number of registers, operations such as register-register, as well as the lack of indirect addressing. RISC concept was developed by John Kock (John Cocke) from IBM Research, the name coined by David Patterson (David Patterson). The most common implementation of this architecture is represented by a series of processors, PowerPC, including G3, G4 and G5. Fairly well-known implementation of this architecture - MIPS processors series and Alpha.
MISC-processors

Minimum Instruction Set Computing - minimal instruction set computing. Further development of the ideas the team of Chuck Moore, who believes that the principle of simplicity, the original for RISC processors, too quickly receded into the background. In the heat of the struggle for maximum performance, RISC catch up and overtake many CISC processors by complexity. MISC architecture is based on the stack computation model with a limited number of teams (about 20-30 teams).
Multi-core processors

Contain multiple processing cores in one package (one or more crystals). Processors designed for single copies of the operating system on multiple cores, are highly integrated implementation of the "multiprocessor". At the moment, the mass available processors with two cores, in particular Intel Core 2 Duo Conroe core and Athlon64X2 based microarchitecture K8.

In November 2006, released their first quad-core Intel Core 2 Quad on the core Kentsfield, which is an assembly of two crystals of Conroe in one case. Dual-Core potsessorov includes such things as the availability of logical and physical cores, for example dual-core Intel Core Duo processor consists of one physical core, which in turn is divided into two logical. The Intel Core 2 Duo processor has two physical cores, which significantly affects the speed of his work.

September 10, 2007 were released in the sale of native (in the form of a single chip) processors for servers chetyrehyadernye AMD Quad-Core Opteron, which had in the development code name for AMD Opteron Barselona [1]. November 19, 2007 went on sale chetyrehyaderny processor for home computers, AMD Quad-Core Phenom [2]. These PROCESORS implement new microarchitecture K8L (K10). September 27, 2006 Intel demonstrated a prototype 80-core processor [3]. It is assumed that the mass production of these processors will be possible until the transition to 32-nanometer process technology, and this in turn is expected by 2010.

Stages of the cycle of commands:
processor puts the number stored in the register counter, on the address bus, and gives the memory read command;
exhibited a number of memory address, memory address, and receiving a read command, exposes content stored at that address on the data bus, and reports on availability;
processor receives a number from the data bus, interprets it as a command (machine instruction) from the system command and executes it;
if the last command is the command transfer, the processor increments (assuming that the length of each team is equal to unity), the number stored in counter commands, there is formed as a result of the command address;
again satisfied with the first paragraph.
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